Abhay Saxena ¹, Ashutosh Bhatt ², Parth Gautam ¹, Puneet Verma ³, Chandrashekhar Patel ¹

Affiliations
1 Dev Sanskriti Vishwa Vidayalaya, Haridwar, Uttarakhand-249411, IN
2 Department of Computer Science, BIAS, Bhimtal, Uttarakhand-263136, IN
3 Department of Computer Science, SIT, Pithoragarh, IN

Abstract

Green computing is making revolution by bringing high speed processor with less power consumption. Our paper is based on this philosophy. Objectives: To come out High Performance FIFO for processor by minimizing the power consumption. Methods/Statistical Analysis: To make FPGA based design of FIFO we used voltages and frequency scaling techniques. Keeping voltage constant at 2.3 volt we varied frequency from 20MHz to 250MHz and for other experiment we kept the frequency constant and varies voltages from 1volt to 2.3 volt. Findings: The power consumption is reduced to 95.79% on voltage scaling where as there is a 4.38% less power consumption on frequency scaling. Application/Improvements: It will surely help in futuristic processor development.

Keywords

Field Programmable Gate Array (FPGA), First in First Out (FIFO), Hardware Description Language (HDL), High Performance Design, Voltage Scaling.

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Karthik Kalia ¹, Md. Atiqur Rahman ¹, Dil M. Akbar Hussain ², Abhay Saxena ³, Mandeep Singh Walia ⁴

Affiliations
1 Gyancity Research Lab, Trikuta Nagar, Jammu - 180012, Jammu and Kashmir, IN
2 Aalborg University, DK
3 Dev Sanskriti Vishwavidyalaya, Haridwar - 249411, Uttarakhand, IN
4 Mahant Bachittar Singh College of Engineering and Technology, Jammu - 181101, Jammu and Kashmir, IN

Abstract

Background/Objectives: In this paper we will be discussing about the impact of technology on our daily lives. How everybody is dependent upon technology in one or other way. Methods/Statistical Analysis: Technology has played a significant role in the evolution of the society. Science has produced many new ideas but to harvest those ideas, technology is a must. With the huge requirement of engineering equipment's, the industry needs specialists who can manage and operate these technologies. Detailed information about the merits and demerits of technology is also mentioned in this paper. Findings: Technology has affected the environment on a great scale; in some cases, technology is even replacing human being or use of manpower. So proper counter measures have been mentioned, which can be used to control and limit harmful effect.

Keywords

3 R’s, Advanced Technology, Computation, E-waste, Engineering.

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Bishwajeet Pandey ¹, Md. Atiqur Rahman ¹, Dil M. Akbar Hussain ², Abhay Saxena ³, Bhagwan Das ⁴

Affiliations
1 Gyancity Research Lab, IN
2 Aalborg University, DK
3 Dev Sanskriti Vishwavidyalaya, Haridwar, IN
4 UTHM, MY

Abstract

The 8-bit design is able to process 256 times input combination in compare to 4-bit vedic multiplier, using approximates 6 times basic elements, 2 times IO buffers, approximate 1.5 times total power dissipation. HSTL_I_12, SSTL18_I and LVCMOS12 are the most energy efficient IO standards in HSTL, SSTL and LVCMOS family respectively. Device static power and design static power are two types of static power dissipation. Device static power is also known as Leakage power when the device is on but not configured. Design static power is power dissipation when bit file of design is downloaded on FPGA but there is no switching activity. Design static power dissipation of 8-bit Vedic multiplier is almost double of design static power dissipation of 4-bit Vedic multiplier. Device static (leakage) power dissipation of 8-bit Vedic multiplier is almost equal to device static power dissipation of 4-bit Vedic multiplier on 40nm FPGA.

Keywords

HSTL, IO Standards, LVCMOS, SSTL, Static Power Reduction, Vedic Multiplier, Voltage Scaling.

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Abhay Saxena ¹, Chandrashekhar Patel ¹, M. Sadiq Ali Khan ²

Affiliations
1 Dev Sanskriti Vishvavidyalaya, Haridwar - 249411, Uttarakhand, IN
2 Department of Computer Science, University of Karachi, PK

Abstract

In our work we have designed CRC using the LVCMOS IO standards which are stands for Low Voltage Complementary Metal Oxide Semiconductor. In this work we have worked with four kinds of LVCMOS (LVCMOS 12, LVCMOS 15, LVCMOS 18, LVCMOS 25). For LVCMOS 12 when we scaled down the frequency form 50GHz to 10 GHz we found 64.41% reduction in total power. For LVCMOS 15 when we change down the frequency form 50GHz to 10GHz we found 67.58% reduction in total power. For LVCMOS 18 when we scaled down the frequency form 50GHz to 10 GHz we found 69.54% reduction in total power. In last when we reduced the frequency form 50GHz to 10GHz in LVCMOS 25 we found 64.41% reduction in total power. Our CRC design is implemented on Virtex-6 FPGA family.

Keywords

40 nm FPGA, CRC, Energy Efficient, Low Power, LVCMOS IO Standard.

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